Lab 02: Paging and Address Translation (w/ Unit Tests)

Operating Systems Lab Exercise
Duration: 90 minutes Language: Java
Testing: JUnit 5

Learning Objectives

By completing this lab, you will be able to:

• Decompose a Logical Address into its constituent Page Number (p) and Offset (d).
• Explain the role of the Page Table in mapping virtual to physical addresses.
• Implement the full Logical-to-Physical Address translation scheme.
• Verify the correctness of memory management logic using JUnit 5 unit tests.
• Identify and simulate the condition that causes a Page Fault.

Project Setup

Clone the repository

git clone https://forgejo.skynet.ie/andrew/cs4023-lab-02.git

Open in IntelliJ IDEA

Ensure JUnit 5 is configured in the project

You should find two files in your project structure: * PagingSimulator.java (Main logic code). * PagingSimulatorTest.java (Unit test code).

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Part A: Address Decomposition (35 Minutes)

In this section, you will focus only on breaking down the Logical Address using the Page Size.

Task A.1: Understand the Decomposer

Open PagingSimulator.java in the project.

Your initial focus is on the decomposeAddress method and the DecompositionResult helper class.

• Examine the logic used to calculate the Page Number (p) (integer division) and the Offset (d) (modulo operator).

Task A.2: Run Decomposition Unit Tests

Locate the testDecomposition... methods in PagingSimulatorTest.java. These tests verify the math behind the decomposition.

1. Run all unit tests in PagingSimulatorTest.java.
2. Expected Outcome: The tests prefixed with testDecomposition... should all PASS.

Task A.3: Checkpoint Questions

Answer the following questions based on your code and test results:

1. For a Page Size of 4096 bytes (4 KB), what is the maximum possible value for the Offset (d)? What happens if an address results in an Offset greater than this maximum?
2. Given a 16-bit address space (0 to 65,535) and a Page Size of 256 bytes, how many bits are used for the Offset, and how many are used for the Page Number?

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Part B: Full Address Translation (45 Minutes)

In this section, you will complete the implementation of the main memory translation process.

Task B.1: Implement Address Translation

The PagingSimulator.java code contains the partially implemented translateAddress method and the static PAGE_TABLE.

1. Complete the logic inside the translateAddress method (the section marked // --- START YOUR IMPLEMENTATION HERE ---).
2. The method must retrieve the Frame Number (f) from the PAGE_TABLE using the calculated Page Number (p).
3. If p is in the table, calculate the Physical Address (P) using the formula: P = (f \times \text{Page Size}) + d
4. If p is not in the table, the function must return -1 to signal a Page Fault.

Task B.2: Run Translation Unit Tests

Locate the testSuccessfulTranslation... and testPageFault methods in PagingSimulatorTest.java.

1. Run all unit tests in PagingSimulatorTest.java again.
2. Expected Outcome: All tests, including the decomposition tests from Part A, should now PASS. If a translation test fails, debug your translateAddress implementation.

Task B.3: Checkpoint Questions

Answer the following questions based on the full translation process:

1. In your simulation, what specific action (or lack thereof) in the code causes the testPageFault unit test to pass? How does this simulate the real operating system's behavior?
2. In the PAGE_TABLE structure, why is the Page Number (the key) explicitly stored, rather than just using an array where the index implies the Page Number? (Hint: Think about memory efficiency and multi-level paging).
3. What specific concept covered in the previous lecture (Dynamic Loading) is facilitated by the non-contiguous nature of memory allocation provided by Paging?

That's all for today's lab, well done everybody!